We are pleased to announce the availability of the first public beta
release of the M5 simulator.
M5 is a modular platform for computer system architecture research,
encompassing system-level architecture as well as processor
microarchitecture. Key features include interchangeable CPU models,
including a detailed OOO SMT processor model; a detailed, event-driven
memory system; multiprocessor capability; full-system capability;
multi-system (client/server network) modeling capability; and pervasive
object orientation. For more information on M5, see
To download M5 source code, see http://sourceforge.net/projects/m5sim.
If you are interested in future announcements regarding M5 releases,
please subscribe to the M5 announcement mailing list at
If you have any questions about M5 in general or this release
specifically, please send them to the M5 users mailing list at
Although the code is publicly available, we are attempting informally to
keep the distribution of this beta release limited. Feel free to
forward this message to specific individuals who you believe may be
interested, but please do not broadcast this announcement indiscriminately.
We plan to follow up with a broader release sometime after the ISCA
on behalf of the M5 Development Team